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| SCIOPTA NEWS |
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| Bottmingen/Basel, February 9 2011 |
| SCIOPTA RTOS for Freescale's® MPC5643L Microcontroller |
SCIOPTA Systems AG is announcing the immediate availability of the SCIOPTA Real-Time Operating Systems for the MPC5643L processor.
The SCIOPTA MPC5643L RTOS is written in highly optimized assembler and specifically tuned for the MPC5643L processors. This results in a very high performance and a low memory footprint. The MPC5510 kernel is Power ArchitectureTM Book E-compliant (e200 core).
SCIOPTA MPC5643L is certified according to IEC61508 up to SIL3.
Beside the fast Real-Time Kernel there is IPS (Internet Protocols, TCP/IP), IPS Applications (Web Server, DHCP, DNS, SMTP, Telnet, TFTP etc.), SFFS (Flash File Systems), USB support, embedded GUI graphics support and the DRUID System Level Debugger available.
SCIOPTA is royalty free and supports actually the C/C++ compilers and environments from GNU GCC and Windriver/DIAB. A precompiled version of GCC is included on the SCIOPTA CD.
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| Freescale's® MPC5643L |
The MPC5643L series microcontrollers are system-on-chip devices that are built on Power Architecture® technology, are 100% user-mode compatible with the classic Power Architecture instruction set, contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP), and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system.
All devices in this family are built around a dual core safety platform with an innovative safety concept targeting ISO 26262 ASILD and IEC 61508 SIL3 integrity levels. In order to minimize additional software and module level features to reach this target, on-chip redundancy is offered for the critical components of the microcontroller (CPU core, DMA controller, interrupt controller, crossbar bus system, memory protection unit, flash memory and RAM controllers, peripheral bus bridge, system timers, and watchdog timer). Lock Step Redundancy Checking Units are implemented at each output of this Sphere of Replication (SoR). ECC is available for on-chip RAM and flash memories. A programmable fault collection and control unit monitors the integrity status of the device and provides flexible safe state control.
The host processor core of the MPC5643L is the latest CPU from the e200 family of compatible Power Architecture cores.
The peripheral set is compatible with the MPC560xP family, providing high-end electrical motor control capability with very low CPU intervention, thanks to the on-chip Cross Triggering Unit (CTU). This device incorporates high-performance 90 nm embedded flash-memory technology to provide substantial cost reduction per feature and significant performance improvement. |
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| About SCIOPTA |
SCIOPTA Systems develops, sells, supports and maintains systems software for safety-critical embedded applications.
This includes real-time operating systems, network software, file systems, software for interface bus systems, board support packages and other system software.
SCIOPTA is a message based real-time operating system with many built-in safety functions and is therefore very well suited for software forming part of safety-related systems. SCIOPTA is certified by TÜV to IEC61508 at Safety Integrity Level 3 (SIL3).
But SCIOPTA is more than just an RTOS. It is a new and modern approach to design embedded systems. The direct message passing method allows easy and time-saving design of robust and secure systems. Applications based on the SCIOPTA Method can cover small static SoC designs to large dynamic distributed systems. |
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